One class of nonvolatile memory devices includes electrically erasable programmable read only memory (EEPROM), which may be used in many applications including embedded applications and mass storage applications. In typical embedded applications, an EEPROM device may be used to provide code storage in personal computers or mobile phones, for example, where fast random access read times may be required. Typical mass storage applications include memory card applications requiring high capacity and low cost.
One category of EEPROM devices includes NAND-type flash memories, which can provide a low cost and high capacity alternative to other forms of nonvolatile memory. FIG. 1A illustrates a conventional flash memory array 10 having a plurality of NAND-type strings therein. Each of these NAND-type strings includes a plurality of EEPROM cells, which are associated with respective even and odd bit lines (BL0_e, BL0_o, . . . , BLn_e, BLn_o). These bit lines are connected to a page buffer 12 having a plurality of buffer circuits (PB0, . . . , PBn) therein. Each EEPROM cell includes a floating gate electrode (or charge trap layer) and a control gate electrode, which is electrically connected to a respective word line (WL0, WL1, . . . , WLn). Access to each NAND string is enabled by driving a string select line (SSL) to a logic 1 voltage during reading and programming operations. Each NAND string also includes a respective ground select transistor, which is electrically connected to a ground select line (GSL).
As illustrated by FIG. 1B, the EEPROM cells within the flash memory array 10 of FIG. 1A may be cells that support a single programmed state. EEPROM cells that support only a single programmed state are typically referred to as single level cells (SLC). In particular, an SLC may support an erased state, which may be treated as a logic 1 storage value, and a programmed state, which may be treated as a logic 0 storage value. The SLC may have a negative threshold voltage (Vth) when erased (e.g., −3V<Vth<−1V) and a positive threshold voltage when programmed (e.g., 1V<Vth<3V). This programmed state may be achieved by setting the bit line BL to a logic 0 value (e.g., 0 Volts), applying a program voltage (Vpgm) to a selected EEPROM cell and applying a pass voltage (Vpass) to the unselected EEPROM cells within a string, as illustrated by FIG. 1C. In addition, during programming the NAND string may be enabled by applying a positive voltage (e.g., power supply voltage Vdd) to the string select line (SSL) and a ground voltage (e.g., 0 Volts) to the ground select line (GSL).
Moreover, the programmed state or erased state of an EEPROM cell may be detected by performing a read operation on a selected cell. As illustrated by FIG. 1D, a NAND string will operate to discharge a precharged bit line BL when a selected cell is in an erased state and the selected word line voltage (e.g., 0 Volts) is greater than the threshold voltage of the selected cell. However, when a selected cell is in a programmed state, the corresponding NAND string will provide an open circuit to the precharged bit line BL because the selected word line voltage (e.g., 0 Volts) is less than the threshold voltage of the selected cell and the selected cell remains “off”. Other aspects of NAND-type flash memories are disclosed in an article by Jung et al., entitled “A 3.3 Volt Single Power Supply 16-Mb Nonvolatile Virtual DRAM Using a NAND Flash Memory Technology,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1748-1757, November (1997), the disclosure of which is hereby incorporated herein by reference.
FIG. 2A is an electrical schematic of a conventional charge trap flash (CTF) memory array 10′ having a plurality of NAND-type strings of charge trap memory cells therein that are electrically coupled to respective bit lines BL0-BLm. Each of the NAND-type strings in the array 10′ includes a string selection transistor, a plurality of memory cell transistors and a ground selection transistor. The string selection transistors are responsive to a string selection signal provided on a string selection line SSL and the ground selection transistors are responsive to a ground selection signal provided on a ground selection line GSL. The source terminals of the ground selection transistors are connected to a common source line CSL, which may be biased at a ground reference potential (e.g., GND=Vss=0 Volts), and the drain terminals of the string selection transistors are connected to respective bit lines. Each row of memory cell transistors within the array 10′ is electrically coupled to a corresponding word line (shown as WL0-WLn).
FIG. 2B is a cross-sectional view of a NAND-type string of transistors within the array 10′. These transistors are formed within a semiconductor region 110, which may be a P-well region (PW) within a semiconductor substrate. This semiconductor region 110 forms rectifying junctions with the source/drain regions 140 of the transistors. A multilayer charge trap layer 120 is provided on a surface of the semiconductor region 110. This multilayer charge trap layer 120 includes a tunnel layer 122, a charge storage layer 124 and a blocking layer 126. The string selection lines, ground selection lines and word lines may be formed as metallization patterns 130 that extend on the multilayer charge trap layer 120, as illustrated. The string selection transistors and ground selection transistors within each NAND-type string may be configured as disclosed at FIGS. 2, 5-6 and 10 of U.S. Pat. No. 6,881,626 Lee et al., entitled “Method of Fabricating A Non-Volatile Memory Device With a String Select Gate,” the disclosure of which is hereby incorporated herein by reference.
An interlayer insulating layer 145 is provided on the metallization patterns 130. This interlayer insulating layer 145 may be patterned to define bit line openings therein that expose corresponding drain regions 140 of the string selection transistors. These openings are filled with bit line plugs 150, which are electrically connected to corresponding bit lines BL. Similarly, the interlayer insulating layer 145, which may be a composite of multiple insulating layers, includes a common source line CSL that is electrically connected to corresponding source regions 140 of the ground selection transistors within the memory array 10′. These and other aspects of the CTF memory array 10′ are also disclosed in U.S. Pat. No. 6,774,433 to Lee et al., the disclosure of which is hereby incorporated herein by reference. Charge trap flash (CTF) memory cells are also disclosed in U.S. Pat. No. 7,126,185 to Kang et al. and U.S. Pat. Publication No. 2006/0171209 to Sim et al.